1. Field of the Invention
The present invention relates to a comparator, and in particular to a comparator that generates a digital output signal in accordance with an input signal.
2. Background of the Related Art
Current-mode operations have been considered as an alternative in analog circuit designs with high speed and/or low power consumption VLSI technology. Comparators have been, and are still, an important building block in electronic systems including data o converters and other front-end signal processing applications.
FIG. 1 shows a circuit of a related art current comparator disclosed in Electronics Letters, Jan. 6, 1994 Vol. 30 No. 1. As shown in FIG. 1, MOS transistors M1 and M2 form a class B voltage buffer, and MOS transistors M3 to M6 form two inverting amplifiers. IIN is an input current, which is the difference between an input signal and reference currents. The inverting amplifiers have three modes of operation.
First, when the input current IIN is positive, voltage V1 at a node 1 pulled high level. This high level voltage V1 is inverted and amplified by a PMOS transistor M3 and an NMOS transistor M4, which causes voltage V2 at a node 2 to go low level. As gate-source voltage VGS1 of the NMOS transistor M1 and gate-source voltage VGS2 of the PMOS transistor M2 are negative, the NMOS transistor M1 is turned off and the PMOS transistor M2 is turned on. In this state, the node 1 is a low impedance node.
When the sign of input current IIN is changed (i.e., a direction of the current IIN is changed), there is insufficient gate drive for the buffer to supply input current IIN, because the NMOS transistor M1 and the PMOS transistor M2 of the buffer are not perfectly in on/off states, respectively. Thus, the node 1 is temporarily a high impedance node.
When the input current IIN is negative, the voltage V1 is pulled low level and the voltage V2 is pulled high level, turning the NMOS transistor M1 on and the PMOS transistor M2 off, the node 1 is low impedance again. The width of this deadband region in the transfer characteristics of the voltage buffer M1 and M2 is determined by the threshold voltage of M1 and M2, and a response time of the comparator increases, as the input current IIN decreases.
The current comparator in FIG. 1 reduced the deadband region by changing the biasing scheme of M1 and M2 from class B to class AB operation. The class AB operation results in smaller voltage swings at node 1 and node 2, and hence faster response times. However, the current comparator requires a complicated bias circuit of class AB to reduce the deadband region, which increases power consumption. Therefore, the current comparator uses nonlinear positive feedback to enhance the response time achieved at the expense of sensitivity and power consumption. The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.